AT91x40
[AT91 Support]

Collaboration diagram for AT91x40:


Detailed Description

Register definitions.


Peripheral Identifiers and Interrupts

#define FIQ_ID   0
 Fast interrupt ID.
#define SWIRQ_ID   1
 Software interrupt ID.
#define US0_ID   2
 USART 0 ID.
#define US1_ID   3
 USART 1 ID.
#define TC0_ID   4
 Timer 0 ID.
#define TC1_ID   5
 Timer 1 ID.
#define TC2_ID   6
 Timer 2 ID.
#define WDI_ID   7
 Watchdog interrupt ID.
#define PIO_ID   8
 Parallel I/O controller ID.
#define IRQ0_ID   16
 External interrupt 0 ID.
#define IRQ1_ID   17
 External interrupt 1 ID.
#define IRQ2_ID   18
 External interrupt 2 ID.

Defines

#define EBI_BASE   0xFFE00000
 EBI base address.
#define SF_BASE   0xFFF00000
 Special function register base address.
#define USART1_BASE   0xFFFCC000
 USART 1 base address.
#define USART0_BASE   0xFFFD0000
 USART 0 base address.
#define TC_BASE   0xFFFE0000
 TC base address.
#define PIO_BASE   0xFFFF0000
 PIO base address.
#define PS_BASE   0xFFFF4000
 PS base address.
#define WD_BASE   0xFFFF8000
 Watch Dog register base address.
#define AIC_BASE   0xFFFFF000
#define PERIPH_RPR_OFF   0x00000030
 Receive pointer register offset.
#define PERIPH_RCR_OFF   0x00000034
 Receive counter register offset.
#define PERIPH_TPR_OFF   0x00000038
 Transmit pointer register offset.
#define PERIPH_TCR_OFF   0x0000003C
 Transmit counter register offset.
#define USART_HAS_PDC


Define Documentation

#define FIQ_ID   0

Fast interrupt ID.

Definition at line 88 of file at91x40.h.

#define SWIRQ_ID   1

Software interrupt ID.

Definition at line 89 of file at91x40.h.

#define US0_ID   2

USART 0 ID.

Definition at line 90 of file at91x40.h.

#define US1_ID   3

USART 1 ID.

Definition at line 91 of file at91x40.h.

#define TC0_ID   4

Timer 0 ID.

Definition at line 92 of file at91x40.h.

#define TC1_ID   5

Timer 1 ID.

Definition at line 93 of file at91x40.h.

#define TC2_ID   6

Timer 2 ID.

Definition at line 94 of file at91x40.h.

#define WDI_ID   7

Watchdog interrupt ID.

Definition at line 95 of file at91x40.h.

#define PIO_ID   8

Parallel I/O controller ID.

Definition at line 96 of file at91x40.h.

#define IRQ0_ID   16

External interrupt 0 ID.

Definition at line 97 of file at91x40.h.

#define IRQ1_ID   17

External interrupt 1 ID.

Definition at line 98 of file at91x40.h.

#define IRQ2_ID   18

External interrupt 2 ID.

Definition at line 99 of file at91x40.h.

#define EBI_BASE   0xFFE00000

EBI base address.

Definition at line 102 of file at91x40.h.

#define SF_BASE   0xFFF00000

Special function register base address.

Definition at line 103 of file at91x40.h.

#define USART1_BASE   0xFFFCC000

USART 1 base address.

Definition at line 104 of file at91x40.h.

#define USART0_BASE   0xFFFD0000

USART 0 base address.

Definition at line 105 of file at91x40.h.

#define TC_BASE   0xFFFE0000

TC base address.

Definition at line 106 of file at91x40.h.

#define PIO_BASE   0xFFFF0000

PIO base address.

Definition at line 107 of file at91x40.h.

#define PS_BASE   0xFFFF4000

PS base address.

Definition at line 108 of file at91x40.h.

#define WD_BASE   0xFFFF8000

Watch Dog register base address.

Definition at line 109 of file at91x40.h.

#define AIC_BASE   0xFFFFF000

AIC base address.

Definition at line 110 of file at91x40.h.

#define PERIPH_RPR_OFF   0x00000030

Receive pointer register offset.

Definition at line 112 of file at91x40.h.

#define PERIPH_RCR_OFF   0x00000034

Receive counter register offset.

Definition at line 113 of file at91x40.h.

#define PERIPH_TPR_OFF   0x00000038

Transmit pointer register offset.

Definition at line 114 of file at91x40.h.

#define PERIPH_TCR_OFF   0x0000003C

Transmit counter register offset.

Definition at line 115 of file at91x40.h.

#define USART_HAS_PDC

Definition at line 117 of file at91x40.h.


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