|
SSC Control Register |
#define | SSC_CR_OFF 0x00000000 |
| Control register offset.
|
#define | SSC_CR (SSC_BASE + SSC_CR_OFF) |
| Control register address.
|
#define | SSC_RXEN 0x00000001 |
| Receive enable.
|
#define | SSC_RXDIS 0x00000002 |
| Receive disable.
|
#define | SSC_TXEN 0x00000100 |
| Transmit enable.
|
#define | SSC_TXDIS 0x00000200 |
| Transmit disable.
|
#define | SSC_SWRST 0x00008000 |
| Software reset.
|
SSC Clock Mode Register |
#define | SSC_CMR_OFF 0x00000004 |
| Clock mode register offset.
|
#define | SSC_CMR (SSC_BASE + SSC_CMR_OFF) |
| Clock mode register address.
|
#define | SSC_DIV_LSB 0 |
| Least significant bit of clock divider.
|
#define | SSC_DIV 0x00000FFF |
| Clock divider.
|
SSC Receive/Transmit Clock Mode Register |
#define | SSC_RCMR_OFF 0x00000010 |
| Receive clock mode register offset.
|
#define | SSC_RCMR (SSC_BASE + SSC_RCMR_OFF) |
| Receive clock mode register address.
|
#define | SSC_TCMR_OFF 0x00000018 |
| Transmit clock mode register offset.
|
#define | SSC_TCMR (SSC_BASE + SSC_TCMR_OFF) |
| Transmit clock mode register address.
|
#define | SSC_CKS 0x00000003 |
| Receive clock selection.
|
#define | SSC_CKS_DIV 0x00000000 |
| Divided clock.
|
#define | SSC_CKS_RK 0x00000001 |
| RK clock signal.
|
#define | SSC_CKS_TK 0x00000002 |
| TK pin.
|
#define | SSC_CKO 0x0000001C |
| Receive clock output mode selection.
|
#define | SSC_CKO_NONE 0x00000000 |
| None.
|
#define | SSC_CKO_CONT 0x00000004 |
| Continous receive clock.
|
#define | SSC_CKO_TRAN 0x00000008 |
| Receive clock only during data transfers.
|
#define | SSC_CKI 0x00000020 |
| Receive clock inversion.
|
#define | SSC_CKG 0x000000C0 |
| Receive clock gating selection.
|
#define | SSC_CKG_NONE 0x00000000 |
| None, continous clock.
|
#define | SSC_CKG_RFL 0x00000040 |
| Continous receive clock.
|
#define | SSC_CKG_RFH 0x00000080 |
| Receive clock only during data transfers.
|
#define | SSC_START 0x00000F00 |
| Receive start selection.
|
#define | SSC_START_CONT 0x00000000 |
| Receive start as soon as enabled.
|
#define | SSC_START_TX 0x00000100 |
| Receive start on transmit start.
|
#define | SSC_START_LOW_RF 0x00000200 |
| Receive start on low level RF.
|
#define | SSC_START_HIGH_RF 0x00000300 |
| Receive start on high level RF.
|
#define | SSC_START_FALL_RF 0x00000400 |
| Receive start on falling edge RF.
|
#define | SSC_START_RISE_RF 0x00000500 |
| Receive start on rising edge RF.
|
#define | SSC_START_LEVEL_RF 0x00000600 |
| Receive start on any RF level change.
|
#define | SSC_START_EDGE_RF 0x00000700 |
| Receive start on any RF edge.
|
#define | SSC_START_COMP0 0x00000800 |
| Receive on compare 0.
|
#define | SSC_STOP 0x00001000 |
| Receive stop selection.
|
#define | SSC_STTDLY 0x00FF0000 |
| Receive start delay.
|
#define | SSC_STTDLY_LSB 16 |
| Least significant bit of receive start delay.
|
#define | SSC_PERIOD 0xFF000000 |
| Receive period divider selection.
|
#define | SSC_PERIOD_LSB 24 |
| Least significant bit of receive period divider selection.
|
SSC Receive/Transmit Frame Mode Registers |
#define | SSC_RFMR_OFF 0x00000014 |
| Receive frame mode register offset.
|
#define | SSC_RFMR (SSC_BASE + SSC_RFMR_OFF) |
| Receive frame mode register address.
|
#define | SSC_TFMR_OFF 0x0000001C |
| Transmit frame mode register offset.
|
#define | SSC_TFMR (SSC_BASE + SSC_TFMR_OFF) |
| Transmit frame mode register address.
|
#define | SSC_DATLEN 0x0000001F |
| Data length.
|
#define | SSC_DATLEN_LSB 0 |
| Least significant bit of data length.
|
#define | SSC_LOOP 0x00000020 |
| Loop mode.
|
#define | SSC_MSBF 0x00000080 |
| Most significant bit first.
|
#define | SSC_DATNB 0x00000F00 |
| Data number per frame.
|
#define | SSC_DATNB_LSB 8 |
| Least significant bit of data number per frame.
|
#define | SSC_FSLEN 0x000F0000 |
| Receive frame sync. length.
|
#define | SSC_FSLEN_LSB 16 |
| Least significant bit of receive frame sync. length.
|
#define | SSC_FSOS 0x00700000 |
| Receive frame sync. output selection.
|
#define | SSC_FSOS_NONE 0x00000000 |
| No frame sync. Line set to input.
|
#define | SSC_FSOS_NEGATIVE 0x00100000 |
| Negative pulse.
|
#define | SSC_FSOS_POSITIVE 0x00200000 |
| Positive pulse.
|
#define | SSC_FSOS_LOW 0x00300000 |
| Low during transfer.
|
#define | SSC_FSOS_HIGH 0x00400000 |
| High during transfer.
|
#define | SSC_FSOS_TOGGLE 0x00500000 |
| Toggling at each start.
|
#define | SSC_FSEDGE 0x01000000 |
| Frame sync. edge detection.
|
SSC Receive Holding Register |
#define | SSC_RHR_OFF 0x00000020 |
| Receive holding register offset.
|
#define | SSC_RHR (SSC_BASE + SSC_RHR_OFF) |
| Receive holding register address.
|
SSC Transmit Holding Register |
#define | SSC_THR_OFF 0x00000024 |
| Transmit holding register offset.
|
#define | SSC_THR (SSC_BASE + SSC_THR_OFF) |
| Transmit holding register address.
|
SSC Receive Sync. Holding Register |
#define | SSC_RSHR_OFF 0x00000030 |
| Receive sync. holding register offset.
|
#define | SSC_RSHR (SSC_BASE + SSC_RSHR_OFF) |
| Receive sync. holding register address.
|
SSC Transmit Sync. Holding Register |
#define | SSC_TSHR_OFF 0x00000034 |
| Transmit sync. holding register offset.
|
#define | SSC_TSHR (SSC_BASE + SSC_TSHR_OFF) |
| Transmit sync. holding register address.
|
SSC Receive Compare 0 Register |
#define | SSC_RC0R_OFF 0x00000038 |
| Receive compare 0 register offset.
|
#define | SSC_RC0R (SSC_BASE + SSC_RC0R_OFF) |
| Receive compare 0 register address.
|
SSC Receive Compare 1 Register |
#define | SSC_RC1R_OFF 0x0000003C |
| Receive compare 1 register offset.
|
#define | SSC_RC1R (SSC_BASE + SSC_RC1R_OFF) |
| Receive compare 1 register address.
|
SSC Status Register |
#define | SSC_SR_OFF 0x00000040 |
| Status register offset.
|
#define | SSC_SR (SSC_BASE + SSC_SR_OFF) |
| Status register address.
|
#define | SSC_TXRDY 0x00000001 |
| Transmit ready.
|
#define | SSC_TXEMPTY 0x00000002 |
| Transmit empty.
|
#define | SSC_ENDTX 0x00000004 |
| End of transmission.
|
#define | SSC_TXBUFE 0x00000008 |
| Transmit buffer empty.
|
#define | SSC_RXRDY 0x00000010 |
| Receive ready.
|
#define | SSC_OVRUN 0x00000020 |
| Receive overrun.
|
#define | SSC_ENDRX 0x00000040 |
| End of receiption.
|
#define | SSC_RXBUFF 0x00000080 |
| Receive buffer full.
|
#define | SSC_CP0 0x00000100 |
| Compare 0.
|
#define | SSC_CP1 0x00000200 |
| Compare 1.
|
#define | SSC_TXSYN 0x00000400 |
| Transmit sync.
|
#define | SSC_RXSYN 0x00000800 |
| Receive sync.
|
#define | SSC_TXENA 0x00010000 |
| Transmit enable.
|
#define | SSC_RXENA 0x00020000 |
| Receive enable.
|
SSC Interrupt Enable Register |
#define | SSC_IER_OFF 0x00000044 |
| Interrupt enable register offset.
|
#define | SSC_IER (SSC_BASE + SSC_IER_OFF) |
| Interrupt enable register address.
|
SSC Interrupt Disable Register |
#define | SSC_IDR_OFF 0x00000048 |
| Interrupt disable register offset.
|
#define | SSC_IDR (SSC_BASE + SSC_IDR_OFF) |
| Interrupt disable register address.
|
SSC Interrupt Mask Register |
#define | SSC_IMR_OFF 0x0000004C |
| Interrupt mask register offset.
|
#define | SSC_IMR (SSC_BASE + SSC_IMR_OFF) |
| Interrupt mask register address.
|