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Frame Number Register |
#define | UDP_NUM_OFF 0x00000000 |
#define | UDP_NUM (UDP_BASE + UDP_NUM_OFF) |
#define | UDP_FRM_NUM (0x07FF << 0) |
| Mask: Frame Number as Defined in the Packet Field Formats.
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#define | UDP_FRM_ERR _BV(16) |
| Frame Error.
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#define | UDP_FRM_OK _BV(17) |
| Frame OK.
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Global State Register |
#define | UDP_GLBSTATE_OFF 0x00000004 |
#define | UDP_GLBSTATE (UDP_BASE + UDP_GLBSTATE_OFF) |
#define | UDP_FADDEN _BV(0) |
| Function Address Enable.
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#define | UDP_CONFG _BV(1) |
| Configured.
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Function Address Register |
#define | UDP_FADDR_OFF 0x00000008 |
#define | UDP_FADDR (UDP_BASE + UDP_FADDR_OFF) |
#define | UDP_FADD (0x7F << 0) |
| Mask: Function Address Value.
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#define | UDP_FEN _BV(8) |
| Function Enable.
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Interrup Enable Register |
#define | UDP_IER_OFF 0x00000010 |
#define | UDP_IER (UDP_BASE + UDP_IER_OFF) |
#define | UDP_EPINT0 _BV( 0) |
| Endpoint 0 Interrupt.
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#define | UDP_EPINT1 _BV( 1) |
| Endpoint 0 Interrupt.
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#define | UDP_EPINT2 _BV( 2) |
| Endpoint 2 Interrupt.
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#define | UDP_EPINT3 _BV( 3) |
| Endpoint 3 Interrupt.
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#define | UDP_EPINT4 _BV( 4) |
| Endpoint 4 Interrupt.
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#define | UDP_EPINT5 _BV( 5) |
| Endpoint 5 Interrupt.
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#define | UDP_RXSUSP _BV( 8) |
| USB Suspend Interrupt.
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#define | UDP_RXRSM _BV( 9) |
| USB Resume Interrupt.
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#define | UDP_EXTRSM _BV(10) |
| USB External Resume Interrupt.
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#define | UDP_SOFINT _BV(11) |
| USB Start Of frame Interrupt.
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#define | UDP_ENDBUSRES _BV(12) |
| USB End Of Bus Reset Interrupt.
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#define | UDP_WAKEUP _BV(13) |
| USB Resume Interrupt.
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Interrup Disable Register |
#define | UDP_IDR_OFF 0x00000014 |
#define | UDP_IDR (UDP_BASE + UDP_IDR_OFF) |
Interrup Mask Register |
#define | UDP_IMR_OFF 0x00000018 |
#define | UDP_IMR (UDP_BASE + UDP_IMR_OFF) |
Interrup Status Register |
#define | UDP_ISR_OFF 0x0000001C |
#define | UDP_ISR (UDP_BASE + UDP_ISR_OFF) |
Interrup Clear Register |
#define | UDP_ICR_OFF 0x00000020 |
#define | UDP_ICR (UDP_BASE + UDP_ICR_OFF) |
Reset Endpoint Register |
#define | UDP_RST_EP_OFF 0x00000028 |
#define | UDP_RST_EP (UDP_BASE + UDP_RST_EP_OFF) |
#define | UDP_EP0 _BV(0) |
| Reset Endpoint 0.
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#define | UDP_EP1 _BV(1) |
| Reset Endpoint 1.
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#define | UDP_EP2 _BV(2) |
| Reset Endpoint 2.
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#define | UDP_EP3 _BV(3) |
| Reset Endpoint 3.
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#define | UDP_EP4 _BV(4) |
| Reset Endpoint 3.
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#define | UDP_EP5 _BV(5) |
| Reset Endpoint 3.
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Endpoint Control and Status Register |
#define | UDP_CSR_OFF 0x00000030 |
#define | UDP_CSR (UDP_BASE + UDP_CSR_OFF) |
#define | UDP_EP0_CSR (UDP_CSR + 0x00000000) |
| Endpoint 0 CSR Register.
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#define | UDP_EP1_CSR (UDP_CSR + 0x00000004) |
| Endpoint 1 CSR Register.
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#define | UDP_EP2_CSR (UDP_CSR + 0x00000008) |
| Endpoint 2 CSR Register.
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#define | UDP_EP3_CSR (UDP_CSR + 0x0000000C) |
| Endpoint 3 CSR Register.
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#define | UDP_EP4_CSR (UDP_CSR + 0x00000010) |
| Endpoint 4 CSR Register.
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#define | UDP_EP5_CSR (UDP_CSR + 0x00000014) |
| Endpoint 5 CSR Register.
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#define | UDP_TXCOMP _BV(0) |
| Generates an IN packet with data previously written in the DPR.
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#define | UDP_RX_DATA_BK0 _BV(1) |
| Receive Data Bank 0.
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#define | UDP_RXSETUP _BV(2) |
| Sends STALL to the Host (Control endpoints).
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#define | UDP_STALL_SEND_ISOERROR _BV(3) |
| STALL send / Isochronous error (Isochronous endpoints).
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#define | UDP_TXPKTRDY _BV(4) |
| Transmit Packet Ready.
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#define | UDP_FORCESTALL _BV(5) |
| Force Stall (used by Control, Bulk and Isochronous endpoints).
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#define | UDP_RX_DATA_BK1 _BV(6) |
| Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
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#define | UDP_DIR _BV(7) |
| Transfer Direction.
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#define | UDP_EPTYPE (0x7 << 8) |
| Mask: Endpoint type, 3 BIT.
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#define | UDP_EPTYPE_CTRL (0x0 << 8) |
| Endpoint typeControl.
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#define | UDP_EPTYPE_ISO_OUT (0x1 << 8) |
| Endpoint type Isochronous OUT.
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#define | UDP_EPTYPE_BULK_OUT (0x2 << 8) |
| Endpoint type Bulk OUT.
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#define | UDP_EPTYPE_INT_OUT (0x3 << 8) |
| Endpoint type Interrupt OUT.
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#define | UDP_EPTYPE_ISO_IN (0x5 << 8) |
| Endpoint type Isochronous IN.
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#define | UDP_EPTYPE_BULK_IN (0x6 << 8) |
| Endpoint type Bulk IN.
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#define | UDP_EPTYPE_INT_IN (0x7 << 8) |
| Endpoint type Interrupt IN.
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#define | UDP_DTGLE _BV(11) |
| Data Toggle.
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#define | UDP_EPEDS _BV(15) |
| Endpoint Enable Disable.
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#define | UDP_RXBYTECNT (0x7FF << 16) |
| Mask: Number Of Bytes Available in the FIFO.
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FIFO Data Register |
#define | UDP_FDR_OFF 0x00000050 |
#define | UDP_FDR (UDP_BASE + UDP_FDR_OFF) |
#define | UDP_EP0_FDR (UDP_FDR + 0x00000000) |
| Endpoint 0 FIFO Data Register.
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#define | UDP_EP1_FDR (UDP_FDR + 0x00000004) |
| Endpoint 1 FIFO Data Register.
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#define | UDP_EP2_FDR (UDP_FDR + 0x00000008) |
| Endpoint 2 FIFO Data Register.
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#define | UDP_EP3_FDR (UDP_FDR + 0x0000000C) |
| Endpoint 3 FIFO Data Register.
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#define | UDP_EP4_FDR (UDP_FDR + 0x00000010) |
| Endpoint 4 FIFO Data Register.
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#define | UDP_EP5_FDR (UDP_FDR + 0x00000014) |
| Endpoint 5 FIFO Data Register.
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Tranceiver Control Register |
#define | UDP_TXVC_OFF 0x00000074 |
#define | UDP_TXVC (UDP_BASE + UDP_TXVDIS_OFF) |
#define | UDB_TXVDIS _BV(8) |
| Tranceiver disable).
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