ih_at91uart0.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91uart0.c,v $
00036  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00037  * Include more general header file for ARM.
00038  *
00039  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00040  * First check in.
00041  *
00042  */
00043 
00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046 
00047 #ifndef NUT_IRQPRI_UART0
00048 #define NUT_IRQPRI_UART0  4
00049 #endif
00050 
00051 static int Uart0IrqCtl(int cmd, void *param);
00052 
00053 IRQ_HANDLER sig_UART0 = {
00054 #ifdef NUT_PERFMON
00055     0,                  /* Interrupt counter, ir_count. */
00056 #endif
00057     NULL,               /* Passed argument, ir_arg. */
00058     NULL,               /* Handler subroutine, ir_handler. */
00059     Uart0IrqCtl         /* Interrupt control, ir_ctl. */
00060 };
00061 
00065 static void Uart0IrqEntry(void) __attribute__ ((naked));
00066 void Uart0IrqEntry(void)
00067 {
00068     IRQ_ENTRY();
00069 #ifdef NUT_PERFMON
00070     sig_UART0.ir_count++;
00071 #endif
00072     if (sig_UART0.ir_handler) {
00073         (sig_UART0.ir_handler) (sig_UART0.ir_arg);
00074     }
00075     IRQ_EXIT();
00076 }
00077 
00093 static int Uart0IrqCtl(int cmd, void *param)
00094 {
00095     int rc = 0;
00096     u_int *ival = (u_int *)param;
00097     int enabled = inr(AIC_IMR) & _BV(US0_ID);
00098 
00099     /* Disable interrupt. */
00100     if (enabled) {
00101         outr(AIC_IDCR, _BV(US0_ID));
00102     }
00103 
00104     switch(cmd) {
00105     case NUT_IRQCTL_INIT:
00106         /* Set the vector. */
00107         outr(AIC_SVR(US0_ID), (unsigned int)Uart0IrqEntry);
00108         /* Initialize to edge triggered with defined priority. */
00109         outr(AIC_SMR(US0_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_UART0);
00110         /* Clear interrupt */
00111         outr(AIC_ICCR, _BV(US0_ID));
00112         break;
00113     case NUT_IRQCTL_STATUS:
00114         if (enabled) {
00115             *ival |= 1;
00116         }
00117         else {
00118             *ival &= ~1;
00119         }
00120         break;
00121     case NUT_IRQCTL_ENABLE:
00122         enabled = 1;
00123         break;
00124     case NUT_IRQCTL_DISABLE:
00125         enabled = 0;
00126         break;
00127     case NUT_IRQCTL_GETPRIO:
00128         *ival = inr(AIC_SMR(US0_ID)) & AIC_PRIOR;
00129         break;
00130     case NUT_IRQCTL_SETPRIO:
00131         outr(AIC_SMR(US0_ID), (inr(AIC_SMR(US0_ID)) & ~AIC_PRIOR) | *ival);
00132         break;
00133 #ifdef NUT_PERFMON
00134     case NUT_IRQCTL_GETCOUNT:
00135         *ival = (u_int)sig_UART0.ir_count;
00136         sig_UART0.ir_count = 0;
00137         break;
00138 #endif
00139     default:
00140         rc = -1;
00141         break;
00142     }
00143 
00144     /* Enable interrupt. */
00145     if (enabled) {
00146         outr(AIC_IECR, _BV(US0_ID));
00147     }
00148     return rc;
00149 }

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