Power Management Controller
[AT91 Support]

Collaboration diagram for Power Management Controller:


Detailed Description

Power management controller registers.


System Clock Enable, Disable and Status Register

#define PMC_SCER_OFF   0x00000000
 System clock enable register offset.
#define PMC_SCER   (PMC_BASE + PMC_SCER_OFF)
 System clock enable register address.
#define PMC_SCDR_OFF   0x00000004
 System clock disable register offset.
#define PMC_SCDR   (PMC_BASE + PMC_SCDR_OFF)
 System clock disable register address.
#define PMC_SCSR_OFF   0x00000008
 System clock status register offset.
#define PMC_SCSR   (PMC_BASE + PMC_SCSR_OFF)
 System clock status register address.
#define PMC_PCK   0x00000001
 Processor clock.
#define PMC_UHP   0x00000040
 USB host port clock.
#define PMC_UDP   0x00000080
 USB device port clock.
#define PMC_PCK0   0x00000100
 Programmable clock 0 output.
#define PMC_PCK1   0x00000200
 Programmable clock 1 output.
#define PMC_PCK2   0x00000400
 Programmable clock 2 output.
#define PMC_PCK3   0x00000800
 Programmable clock 3 output.

Peripheral Clock Enable, Disable and Status Register

#define PMC_PCER_OFF   0x00000010
 Peripheral clock enable register offset.
#define PMC_PCER   (PMC_BASE + PMC_PCER_OFF)
 Peripheral clock enable register address.
#define PMC_PCDR_OFF   0x00000014
 Peripheral clock disable register offset.
#define PMC_PCDR   (PMC_BASE + PMC_PCDR_OFF)
 Peripheral clock disable register address.
#define PMC_PCSR_OFF   0x00000018
 Peripheral clock status register offset.
#define PMC_PCSR   (PMC_BASE + PMC_PCSR_OFF)
 Peripheral clock status register address.

Clock Generator Main Oscillator Register

#define CKGR_MOR_OFF   0x00000020
 Main oscillator register offset.
#define CKGR_MOR   (PMC_BASE + CKGR_MOR_OFF)
 Main oscillator register address.
#define CKGR_MOSCEN   0x00000001
 Main oscillator enable.
#define CKGR_OSCBYPASS   0x00000002
 Main oscillator bypass.
#define CKGR_OSCOUNT   0x0000FF00
 Main oscillator start-up time mask.
#define CKGR_OSCOUNT_LSB   8
 Main oscillator start-up time LSB.

Clock Generator Main Clock Frequency Register

#define CKGR_MCFR_OFF   0x00000024
 Main clock frequency register offset.
#define CKGR_MCFR   (PMC_BASE + CKGR_MCFR_OFF)
 Main clock frequency register address.
#define CKGR_MAINF   0x0000FFFF
 Main clock frequency mask mask.
#define CKGR_MAINF_OFF   0
 Main clock frequency mask LSB.
#define CKGR_MAINRDY   0x00010000
 Main clock ready.

PLL Registers

#define CKGR_DIV   0x000000FF
 Divider.
#define CKGR_DIV_LSB   0
 Least significant bit of the divider.
#define CKGR_DIV_0   0x00000000
 Divider output is 0.
#define CKGR_DIV_BYPASS   0x00000001
 Divider is bypassed.
#define CKGR_PLLCOUNT   0x00003F00
 PLL counter mask.
#define CKGR_PLLCOUNT_LSB   8
 PLL counter LSB.
#define CKGR_OUT   0x0000C000
 PLL output frequency range.
#define CKGR_OUT_0   0x00000000
 Please refer to the PLL datasheet.
#define CKGR_OUT_1   0x00004000
 Please refer to the PLL datasheet.
#define CKGR_OUT_2   0x00008000
 Please refer to the PLL datasheet.
#define CKGR_OUT_3   0x0000C000
 Please refer to the PLL datasheet.
#define CKGR_MUL   0x07FF0000
 PLL multiplier.
#define CKGR_MUL_LSB   16
 Least significant bit of the PLL multiplier.
#define CKGR_USBDIV   0x30000000
 Divider for USB clocks.
#define CKGR_USBDIV_1   0x00000000
 Divider output is PLL clock output.
#define CKGR_USBDIV_2   0x10000000
 Divider output is PLL clock output divided by 2.
#define CKGR_USBDIV_4   0x20000000
 Divider output is PLL clock output divided by 4.

Master Clock Register

#define PMC_MCKR_OFF   0x00000030
 Master clock register offset.
#define PMC_MCKR   (PMC_BASE + PMC_MCKR_OFF)
 Master clock register address.
#define PMC_ACKR_OFF   0x00000034
 Application clock register offset.
#define PMC_ACKR   (PMC_BASE + PMC_ACKR_OFF)
 Application clock register address.
#define PMC_PCKR0_OFF   0x00000040
 Programmable clock 0 register offset.
#define PMC_PCKR0   (PMC_BASE + PMC_PCKR0_OFF)
 Programmable clock 0 register address.
#define PMC_PCKR1_OFF   0x00000044
 Programmable clock 1 register offset.
#define PMC_PCKR1   (PMC_BASE + PMC_PCKR1_OFF)
 Programmable clock 1 register address.
#define PMC_PCKR2_OFF   0x00000048
 Programmable clock 2 register offset.
#define PMC_PCKR2   (PMC_BASE + PMC_PCKR2_OFF)
 Programmable clock 2 register address.
#define PMC_PCKR3_OFF   0x0000004C
 Programmable clock 3 register offset.
#define PMC_PCKR3   (PMC_BASE + PMC_PCKR3_OFF)
 Programmable clock 3 register address.
#define PMC_CSS   0x00000003
 Clock selection mask.
#define PMC_CSS_SLOW_CLK   0x00000000
 Slow clock selected.
#define PMC_CSS_MAIN_CLK   0x00000001
 Main clock selected.
#define PMC_PRES   0x0000001C
 Clock prescaler mask.
#define PMC_PRES_LSB   2
 Clock prescaler LSB.
#define PMC_PRES_CLK   0x00000000
 Selected clock, not divided.
#define PMC_PRES_CLK_2   0x00000004
 Selected clock divided by 2.
#define PMC_PRES_CLK_4   0x00000008
 Selected clock divided by 4.
#define PMC_PRES_CLK_8   0x0000000C
 Selected clock divided by 8.
#define PMC_PRES_CLK_16   0x00000010
 Selected clock divided by 16.
#define PMC_PRES_CLK_32   0x00000014
 Selected clock divided by 32.
#define PMC_PRES_CLK_64   0x00000018
 Selected clock divided by 64.

Power Management Status and Interrupt Registers

#define PMC_IER_OFF   0x00000060
 Interrupt enable register offset.
#define PMC_IER   (PMC_BASE + PMC_IER_OFF)
 Interrupt enable register address.
#define PMC_IDR_OFF   0x00000064
 Interrupt disable register offset.
#define PMC_IDR   (PMC_BASE + PMC_IDR_OFF)
 Interrupt disable register address.
#define PMC_SR_OFF   0x00000068
 Status register offset.
#define PMC_SR   (PMC_BASE + PMC_SR_OFF)
 Status register address.
#define PMC_IMR_OFF   0x0000006C
 Interrupt mask register offset.
#define PMC_IMR   (PMC_BASE + PMC_IMR_OFF)
 Interrupt mask register address.
#define PMC_MOSCS   0x00000001
 Main oscillator.
#define PMC_MCKRDY   0x00000008
 Master clock ready.
#define PMC_OSC_SEL   0x00000080
 Slow clock oscillator selection.
#define PMC_PCKRDY0   0x00000100
 Programmable clock 0 ready.
#define PMC_PCKRDY1   0x00000200
 Programmable clock 1 ready.
#define PMC_PCKRDY2   0x00000400
 Programmable clock 2 ready.
#define PMC_PCKRDY3   0x00000800
 Programmable clock 3 ready.


Define Documentation

#define PMC_SCER_OFF   0x00000000

System clock enable register offset.

Definition at line 72 of file at91_pmc.h.

#define PMC_SCER   (PMC_BASE + PMC_SCER_OFF)

System clock enable register address.

Definition at line 73 of file at91_pmc.h.

#define PMC_SCDR_OFF   0x00000004

System clock disable register offset.

Definition at line 74 of file at91_pmc.h.

#define PMC_SCDR   (PMC_BASE + PMC_SCDR_OFF)

System clock disable register address.

Definition at line 75 of file at91_pmc.h.

#define PMC_SCSR_OFF   0x00000008

System clock status register offset.

Definition at line 76 of file at91_pmc.h.

#define PMC_SCSR   (PMC_BASE + PMC_SCSR_OFF)

System clock status register address.

Definition at line 77 of file at91_pmc.h.

#define PMC_PCK   0x00000001

Processor clock.

Definition at line 79 of file at91_pmc.h.

#define PMC_UHP   0x00000040

USB host port clock.

Definition at line 80 of file at91_pmc.h.

#define PMC_UDP   0x00000080

USB device port clock.

Definition at line 81 of file at91_pmc.h.

#define PMC_PCK0   0x00000100

Programmable clock 0 output.

Definition at line 82 of file at91_pmc.h.

#define PMC_PCK1   0x00000200

Programmable clock 1 output.

Definition at line 83 of file at91_pmc.h.

#define PMC_PCK2   0x00000400

Programmable clock 2 output.

Definition at line 84 of file at91_pmc.h.

#define PMC_PCK3   0x00000800

Programmable clock 3 output.

Definition at line 85 of file at91_pmc.h.

#define PMC_PCER_OFF   0x00000010

Peripheral clock enable register offset.

Definition at line 90 of file at91_pmc.h.

#define PMC_PCER   (PMC_BASE + PMC_PCER_OFF)

Peripheral clock enable register address.

Definition at line 91 of file at91_pmc.h.

Referenced by At91Spi0Init(), NutRegisterTimer(), and TwInit().

#define PMC_PCDR_OFF   0x00000014

Peripheral clock disable register offset.

Definition at line 92 of file at91_pmc.h.

#define PMC_PCDR   (PMC_BASE + PMC_PCDR_OFF)

Peripheral clock disable register address.

Definition at line 93 of file at91_pmc.h.

#define PMC_PCSR_OFF   0x00000018

Peripheral clock status register offset.

Definition at line 94 of file at91_pmc.h.

#define PMC_PCSR   (PMC_BASE + PMC_PCSR_OFF)

Peripheral clock status register address.

Definition at line 95 of file at91_pmc.h.

#define CKGR_MOR_OFF   0x00000020

Main oscillator register offset.

Definition at line 100 of file at91_pmc.h.

#define CKGR_MOR   (PMC_BASE + CKGR_MOR_OFF)

Main oscillator register address.

Definition at line 101 of file at91_pmc.h.

#define CKGR_MOSCEN   0x00000001

Main oscillator enable.

Definition at line 103 of file at91_pmc.h.

#define CKGR_OSCBYPASS   0x00000002

Main oscillator bypass.

Definition at line 104 of file at91_pmc.h.

#define CKGR_OSCOUNT   0x0000FF00

Main oscillator start-up time mask.

Definition at line 105 of file at91_pmc.h.

#define CKGR_OSCOUNT_LSB   8

Main oscillator start-up time LSB.

Definition at line 106 of file at91_pmc.h.

#define CKGR_MCFR_OFF   0x00000024

Main clock frequency register offset.

Definition at line 111 of file at91_pmc.h.

#define CKGR_MCFR   (PMC_BASE + CKGR_MCFR_OFF)

Main clock frequency register address.

Definition at line 112 of file at91_pmc.h.

#define CKGR_MAINF   0x0000FFFF

Main clock frequency mask mask.

Definition at line 114 of file at91_pmc.h.

#define CKGR_MAINF_OFF   0

Main clock frequency mask LSB.

Definition at line 115 of file at91_pmc.h.

#define CKGR_MAINRDY   0x00010000

Main clock ready.

Definition at line 116 of file at91_pmc.h.

#define CKGR_DIV   0x000000FF

Divider.

Definition at line 131 of file at91_pmc.h.

#define CKGR_DIV_LSB   0

Least significant bit of the divider.

Definition at line 132 of file at91_pmc.h.

#define CKGR_DIV_0   0x00000000

Divider output is 0.

Definition at line 133 of file at91_pmc.h.

#define CKGR_DIV_BYPASS   0x00000001

Divider is bypassed.

Definition at line 134 of file at91_pmc.h.

#define CKGR_PLLCOUNT   0x00003F00

PLL counter mask.

Definition at line 135 of file at91_pmc.h.

#define CKGR_PLLCOUNT_LSB   8

PLL counter LSB.

Definition at line 136 of file at91_pmc.h.

#define CKGR_OUT   0x0000C000

PLL output frequency range.

Definition at line 137 of file at91_pmc.h.

#define CKGR_OUT_0   0x00000000

Please refer to the PLL datasheet.

Definition at line 138 of file at91_pmc.h.

#define CKGR_OUT_1   0x00004000

Please refer to the PLL datasheet.

Definition at line 139 of file at91_pmc.h.

#define CKGR_OUT_2   0x00008000

Please refer to the PLL datasheet.

Definition at line 140 of file at91_pmc.h.

#define CKGR_OUT_3   0x0000C000

Please refer to the PLL datasheet.

Definition at line 141 of file at91_pmc.h.

#define CKGR_MUL   0x07FF0000

PLL multiplier.

Definition at line 142 of file at91_pmc.h.

#define CKGR_MUL_LSB   16

Least significant bit of the PLL multiplier.

Definition at line 143 of file at91_pmc.h.

#define CKGR_USBDIV   0x30000000

Divider for USB clocks.

Definition at line 144 of file at91_pmc.h.

#define CKGR_USBDIV_1   0x00000000

Divider output is PLL clock output.

Definition at line 145 of file at91_pmc.h.

#define CKGR_USBDIV_2   0x10000000

Divider output is PLL clock output divided by 2.

Definition at line 146 of file at91_pmc.h.

#define CKGR_USBDIV_4   0x20000000

Divider output is PLL clock output divided by 4.

Definition at line 147 of file at91_pmc.h.

#define PMC_MCKR_OFF   0x00000030

Master clock register offset.

Definition at line 152 of file at91_pmc.h.

#define PMC_MCKR   (PMC_BASE + PMC_MCKR_OFF)

Master clock register address.

Definition at line 153 of file at91_pmc.h.

#define PMC_ACKR_OFF   0x00000034

Application clock register offset.

Definition at line 154 of file at91_pmc.h.

#define PMC_ACKR   (PMC_BASE + PMC_ACKR_OFF)

Application clock register address.

Definition at line 155 of file at91_pmc.h.

#define PMC_PCKR0_OFF   0x00000040

Programmable clock 0 register offset.

Definition at line 156 of file at91_pmc.h.

#define PMC_PCKR0   (PMC_BASE + PMC_PCKR0_OFF)

Programmable clock 0 register address.

Definition at line 157 of file at91_pmc.h.

#define PMC_PCKR1_OFF   0x00000044

Programmable clock 1 register offset.

Definition at line 158 of file at91_pmc.h.

#define PMC_PCKR1   (PMC_BASE + PMC_PCKR1_OFF)

Programmable clock 1 register address.

Definition at line 159 of file at91_pmc.h.

#define PMC_PCKR2_OFF   0x00000048

Programmable clock 2 register offset.

Definition at line 160 of file at91_pmc.h.

#define PMC_PCKR2   (PMC_BASE + PMC_PCKR2_OFF)

Programmable clock 2 register address.

Definition at line 161 of file at91_pmc.h.

#define PMC_PCKR3_OFF   0x0000004C

Programmable clock 3 register offset.

Definition at line 162 of file at91_pmc.h.

#define PMC_PCKR3   (PMC_BASE + PMC_PCKR3_OFF)

Programmable clock 3 register address.

Definition at line 163 of file at91_pmc.h.

#define PMC_CSS   0x00000003

Clock selection mask.

Definition at line 165 of file at91_pmc.h.

#define PMC_CSS_SLOW_CLK   0x00000000

Slow clock selected.

Definition at line 166 of file at91_pmc.h.

#define PMC_CSS_MAIN_CLK   0x00000001

Main clock selected.

Definition at line 167 of file at91_pmc.h.

#define PMC_PRES   0x0000001C

Clock prescaler mask.

Definition at line 174 of file at91_pmc.h.

#define PMC_PRES_LSB   2

Clock prescaler LSB.

Definition at line 175 of file at91_pmc.h.

#define PMC_PRES_CLK   0x00000000

Selected clock, not divided.

Definition at line 176 of file at91_pmc.h.

#define PMC_PRES_CLK_2   0x00000004

Selected clock divided by 2.

Definition at line 177 of file at91_pmc.h.

#define PMC_PRES_CLK_4   0x00000008

Selected clock divided by 4.

Definition at line 178 of file at91_pmc.h.

#define PMC_PRES_CLK_8   0x0000000C

Selected clock divided by 8.

Definition at line 179 of file at91_pmc.h.

#define PMC_PRES_CLK_16   0x00000010

Selected clock divided by 16.

Definition at line 180 of file at91_pmc.h.

#define PMC_PRES_CLK_32   0x00000014

Selected clock divided by 32.

Definition at line 181 of file at91_pmc.h.

#define PMC_PRES_CLK_64   0x00000018

Selected clock divided by 64.

Definition at line 182 of file at91_pmc.h.

#define PMC_IER_OFF   0x00000060

Interrupt enable register offset.

Definition at line 193 of file at91_pmc.h.

#define PMC_IER   (PMC_BASE + PMC_IER_OFF)

Interrupt enable register address.

Definition at line 194 of file at91_pmc.h.

#define PMC_IDR_OFF   0x00000064

Interrupt disable register offset.

Definition at line 195 of file at91_pmc.h.

#define PMC_IDR   (PMC_BASE + PMC_IDR_OFF)

Interrupt disable register address.

Definition at line 196 of file at91_pmc.h.

#define PMC_SR_OFF   0x00000068

Status register offset.

Definition at line 197 of file at91_pmc.h.

#define PMC_SR   (PMC_BASE + PMC_SR_OFF)

Status register address.

Definition at line 198 of file at91_pmc.h.

#define PMC_IMR_OFF   0x0000006C

Interrupt mask register offset.

Definition at line 199 of file at91_pmc.h.

#define PMC_IMR   (PMC_BASE + PMC_IMR_OFF)

Interrupt mask register address.

Definition at line 200 of file at91_pmc.h.

#define PMC_MOSCS   0x00000001

Main oscillator.

Definition at line 202 of file at91_pmc.h.

#define PMC_MCKRDY   0x00000008

Master clock ready.

Definition at line 209 of file at91_pmc.h.

#define PMC_OSC_SEL   0x00000080

Slow clock oscillator selection.

Definition at line 210 of file at91_pmc.h.

#define PMC_PCKRDY0   0x00000100

Programmable clock 0 ready.

Definition at line 211 of file at91_pmc.h.

#define PMC_PCKRDY1   0x00000200

Programmable clock 1 ready.

Definition at line 212 of file at91_pmc.h.

#define PMC_PCKRDY2   0x00000400

Programmable clock 2 ready.

Definition at line 213 of file at91_pmc.h.

#define PMC_PCKRDY3   0x00000800

Programmable clock 3 ready.

Definition at line 214 of file at91_pmc.h.


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