at91sam9260.h

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00001 #ifndef _ARCH_ARM_SAM9260_H_
00002 #define _ARCH_ARM_SAM9260_H_
00003 /*
00004  * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * 1. Redistributions of source code must retain the above copyright
00011  *    notice, this list of conditions and the following disclaimer.
00012  * 2. Redistributions in binary form must reproduce the above copyright
00013  *    notice, this list of conditions and the following disclaimer in the
00014  *    documentation and/or other materials provided with the distribution.
00015  * 3. Neither the name of the copyright holders nor the names of
00016  *    contributors may be used to endorse or promote products derived
00017  *    from this software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00020  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00021  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00022  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00023  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00024  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00025  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00026  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00027  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00028  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00029  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00030  * SUCH DAMAGE.
00031  *
00032  * For additional information see http://www.ethernut.de/
00033  */
00034 
00061 #define FLASH_BASE      0x100000UL
00062 #define RAM_BASE        0x200000UL
00063 
00064 #define TC_BASE         0xFFFA0000      
00065 #define UDP_BASE        0xFFFA4000      
00066 #define MCI_BASE        0xFFFA8000      
00067 #define TWI_BASE        0xFFFAC000      
00068 #define USART0_BASE     0xFFFB0000      
00069 #define USART1_BASE     0xFFFB4000      
00070 #define USART2_BASE     0xFFFB8000      
00071 #define SSC_BASE        0xFFFBC000      
00072 #define ISI_BASE        0xFFFC0000      
00073 #define EMAC_BASE       0xFFFC4000      
00074 #define SPI0_BASE       0xFFFC8000      
00075 #define SPI1_BASE       0xFFFCC000      
00076 #define USART3_BASE     0xFFFD0000      
00077 #define USART4_BASE     0xFFFD4000      
00078 #define USART5_BASE     0xFFFD8000      
00079 #define TC345_BASE      0xFFFDC000      
00080 #define ADC_BASE        0xFFFE0000      
00081 #define ECC_BASE        0xFFFFE800      
00082 #define SDRAMC_BASE     0xFFFFEA00      
00083 #define SMC_BASE        0xFFFFEC00      
00084 #define MATRIX_BASE     0xFFFFEE00      
00085 #define CCFG_BASE       0xFFFFEF10      
00086 #define AIC_BASE        0xFFFFF000      
00087 #define DBGU_BASE       0xFFFFF200      
00088 #define PIOA_BASE       0xFFFFF400      
00089 #define PIO_BASE        PIOA_BASE
00090 #define PIOB_BASE       0xFFFFF600      
00091 #define PIOC_BASE       0xFFFFF800      
00092 #define PMC_BASE        0xFFFFFC00      
00093 #define RSTC_BASE       0xFFFFFD00      
00094 #define RTT_BASE        0xFFFFFD20      
00095 #define PIT_BASE        0xFFFFFD30      
00096 #define WDT_BASE        0xFFFFFD40      
00098 #define PERIPH_RPR_OFF  0x00000100      
00099 #define PERIPH_RCR_OFF  0x00000104      
00100 #define PERIPH_TPR_OFF  0x00000108      
00101 #define PERIPH_TCR_OFF  0x0000010C      
00102 #define PERIPH_RNPR_OFF 0x00000110      
00103 #define PERIPH_RNCR_OFF 0x00000114      
00104 #define PERIPH_TNPR_OFF 0x00000118      
00105 #define PERIPH_TNCR_OFF 0x0000011C      
00106 #define PERIPH_PTCR_OFF 0x00000120      
00107 #define PERIPH_PTSR_OFF 0x00000124      
00109 #define PDC_RXTEN       0x00000001      
00110 #define PDC_RXTDIS      0x00000002      
00111 #define PDC_TXTEN       0x00000100      
00112 #define PDC_TXTDIS      0x00000200      
00114 #define DBGU_HAS_PDC
00115 #define SPI_HAS_PDC
00116 #define SSC_HAS_PDC
00117 #define USART_HAS_PDC
00118 #define MCI_HAS_PDC
00119 
00120 #define PIO_HAS_MULTIDRIVER
00121 #define PIO_HAS_PULLUP
00122 #define PIO_HAS_PERIPHERALSELECT
00123 #define PIO_HAS_OUTPUTWRITEENABLE
00124 
00125 #include <arch/arm/at91_tc.h>
00126 #include <arch/arm/at91_us.h>
00127 #include <arch/arm/at91_dbgu.h>
00128 #include <arch/arm/at91_emac.h>
00129 #include <arch/arm/at91_spi.h>
00130 #include <arch/arm/at91_aic.h>
00131 #include <arch/arm/at91_pio.h>
00132 #include <arch/arm/at91_pmc.h>
00133 #include <arch/arm/at91_rstc.h>
00134 #include <arch/arm/at91_wdt.h>
00135 #include <arch/arm/at91_ssc.h>
00136 #include <arch/arm/at91_twi.h>
00137 #include <arch/arm/at91_smc.h>
00138 #include <arch/arm/at91_mci.h>
00139 #include <arch/arm/at91_matrix.h>
00140 #include <arch/arm/at91_ccfg.h>
00141 #include <arch/arm/at91_sdramc.h>
00142 
00145 
00148 #define FIQ_ID      0           
00149 #define PIOA_ID     2           
00150 #define PIOB_ID     3           
00151 #define PIOC_ID     4           
00152 #define ADC_ID      5           
00153 #define US0_ID      6           
00154 #define US1_ID      7           
00155 #define US2_ID      8           
00156 #define MCI_ID      9           
00157 #define UDP_ID      10          
00158 #define TWI_ID      11          
00159 #define SPI0_ID     12          
00160 #define SPI1_ID     13          
00161 #define SSC_ID      14          
00162 #define TC0_ID      17          
00163 #define TC1_ID      18          
00164 #define TC2_ID      19          
00165 #define UHP_ID      20          
00166 #define EMAC_ID     21          
00167 #define ISI_ID      22          
00168 #define US3_ID      23          
00169 #define US4_ID      24          
00170 #define US5_ID      25          
00171 #define TC3_ID      26          
00172 #define TC4_ID      27          
00173 #define TC5_ID      28          
00174 #define IRQ0_ID     29          
00175 #define IRQ1_ID     30          
00176 #define IRQ2_ID     31          
00179 
00180 
00182 #define PA31_SCK0_A         31  
00183 #define PB4_TXD0_A          4   
00184 #define PB5_RXD0_A          5   
00185 #define PB27_CTS0_A         27  
00186 #define PB26_RTS0_A         26  
00187 #define PB25_RI0_A          25  
00188 #define PB22_DSR0_A         22  
00189 #define PB23_DCD0_A         23  
00190 #define PB24_DTR0_A         24  
00192 #define PA29_SCK1_A         29  
00193 #define PB6_TXD1_A          6   
00194 #define PB7_RXD1_A          7   
00195 #define PB29_CTS1_A         29  
00196 #define PB28_RTS1_A         28  
00198 #define PA30_SCK2_A         30  
00199 #define PB8_TXD2_A          8   
00200 #define PB9_RXD2_A          9   
00201 #define PA5_CTS2_A          5   
00202 #define PA4_RTS2_A          4   
00204 #define PC0_SCK3_B          0   
00205 #define PB10_TXD3_A         10  
00206 #define PB11_RXD3_A         11  
00207 #define PC10_CTS3_B         10  
00208 #define PC8_RTS3_B          8   
00210 #define PA31_TXD4_B         31  
00211 #define PA30_RXD4_B         30  
00213 #define PB12_TXD5_A         12  
00214 #define PB13_RXD5_A         13  
00216 
00217 
00219 #define PA0_SPI0_MISO_A     0   
00220 #define PA1_SPI0_MOSI_A     1   
00221 #define PA2_SPI0_SPCK_A     2   
00222 #define PA3_SPI0_NPCS0_A    3   
00223 #define PC11_SPI0_NPCS1_B   11  
00224 #define PC16_SPI0_NPCS2_B   16  
00225 #define PC17_SPI0_NPCS3_B   17  
00227 #define SPI0_PINS           _BV(PA0_SPI0_MISO_A) | _BV(PA1_SPI0_MOSI_A) | _BV(PA2_SPI0_SPCK_A)
00228 #define SPI0_PIO_BASE       PIOA_BASE
00229 #define SPI0_PSR_OFF        PIO_ASR_OFF
00230 
00231 #define SPI0_CS0_PIN        _BV(PA3_SPI0_NPCS0_A)
00232 #define SPI0_CS0_PIO_BASE   PIOA_BASE
00233 #define SPI0_CS0_PSR_OFF    PIO_ASR_OFF
00234 
00235 #define SPI0_CS1_PIN        _BV(PC11_SPI0_NPCS1_B)
00236 #define SPI0_CS1_PIO_BASE   PIOC_BASE
00237 #define SPI0_CS1_PSR_OFF    PIO_BSR_OFF
00238 
00239 #define PB0_SPI1_MISO_A     0   
00240 #define PB1_SPI1_MOSI_A     1   
00241 #define PB2_SPI1_SPCK_A     2   
00242 #define PB3_SPI1_NPCS0_A    3   
00243 #define PC5_SPI1_NPCS1_B    5   
00244 #define PC18_SPI1_NPCS1_B   18  
00245 #define PC4_SPI1_NPCS2_B    4   
00246 #define PC19_SPI1_NPCS2_B   19  
00247 #define PC3_SPI1_NPCS3_B    3   
00248 #define PC20_SPI1_NPCS3_B   20  
00250 #define SPI1_PINS           _BV(PB0_SPI1_MISO_A) | _BV(PB1_SPI1_MOSI_A) | _BV(PB2_SPI1_SPCK_A)
00251 #define SPI1_PIO_BASE       PIOB_BASE
00252 #define SPI1_PSR_OFF        PIO_ASR_OFF
00253 
00254 #define SPI1_CS0_PIN        _BV(PB3_SPI1_NPCS0_A)
00255 #define SPI1_CS0_PIO_BASE   PIOB_BASE
00256 #define SPI1_CS0_PSR_OFF    PIO_ASR_OFF
00257 
00258 #ifndef SPI1_CS3_PIN
00259 #define SPI1_CS3_PIN        _BV(PC3_SPI1_NPCS3_B)
00260 #define SPI1_CS3_PIO_BASE   PIOC_BASE
00261 #define SPI1_CS3_PSR_OFF    PIO_BSR_OFF
00262 #endif
00263 
00268 #define PB20_ISI_D0_B       20  
00269 #define PB21_ISI_D1_B       21  
00270 #define PB22_ISI_D2_B       22  
00271 #define PB23_ISI_D3_B       23  
00272 #define PB24_ISI_D4_B       24  
00273 #define PB25_ISI_D5_B       25  
00274 #define PB26_ISI_D6_B       26  
00275 #define PB27_ISI_D7_B       27  
00276 #define PB10_ISI_D8_B       10  
00277 #define PB11_ISI_D9_B       11  
00278 #define PB12_ISI_D10_B      12  
00279 #define PB13_ISI_D11_B      13  
00280 #define PB28_ISI_PCK_B      28  
00281 #define PB29_ISI_VSYNC_B    29  
00282 #define PB30_ISI_HSYNC_B    30  
00283 #define PB31_ISI_MCK_B      31  
00285 
00286 
00288 #define PA8_MCCK_A          8   
00289 #define PA7_MCCDA_A         7   
00290 #define PA6_MCDA0_A         6   
00291 #define PA9_MCDA1_A         9   
00292 #define PA10_MCDA2_A        10  
00293 #define PA11_MCDA3_A        11  
00294 #define PA1_MCCDB_B         1   
00295 #define PA0_MCDB0_B         0   
00296 #define PA5_MCDB1_B         5   
00297 #define PA4_MCDB2_B         4   
00298 #define PA3_MCDB3_B         3   
00300 
00301 
00303 #define PA10_ETX2_B         10  
00304 #define PA11_ETX3_B         11  
00305 #define PA12_ETX0_A         12  
00306 #define PA13_ETX1_A         13  
00307 #define PA14_ERX0_A         14  
00308 #define PA15_ERX1_A         15  
00309 #define PA16_ETXEN_A        16  
00310 #define PA17_ERXDV_A        17  
00311 #define PA18_ERXER_A        18  
00312 #define PA19_ETXCK_A        19  
00313 #define PA20_EMDC_A         20  
00314 #define PA21_EMDIO_A        21  
00315 #define PA22_ETXER_B        22  
00316 #define PA23_ETX2_B         23  
00317 #define PA24_ETX3_B         24  
00318 #define PA25_ERX2_B         25  
00319 #define PA26_ERX3_B         26  
00320 #define PA27_ERXCK_B        27  
00321 #define PA28_ECRS_B         28  
00322 #define PA29_ECOL_B         29  
00323 #define PC21_EF100_B        21  
00325 
00326 
00328 #define PA22_ADTRG_A        22  
00330 
00331 
00333 #define PB14_DRXD_A         14  
00334 #define PB15_DTXD_A         15  
00336 
00337 
00339 #define PB18_TD0_A          18  
00340 #define PB19_RD0_A          19  
00341 #define PB16_TK0_A          16  
00342 #define PB20_RK0_A          20  
00343 #define PB17_TF0_A          17  
00344 #define PB21_RF0_A          21  
00346 
00347 
00349 #define PA23_TWD_A          23  
00350 #define PA24_TWCK_A         24  
00352 
00353 
00355 #define PA25_TCLK0_A        25  
00356 #define PA26_TIOA0_A        26  
00357 #define PC9_TIOB0_B         9   
00359 #define PB6_TCLK1_B         6   
00360 #define PA27_TIOA1_A        27  
00361 #define PC7_TIOB1_A         7   
00363 #define PB7_TCLK2_B         7   
00364 #define PA28_TIOA2_A        28  
00365 #define PC6_TIOB2_A         6   
00367 #define PB16_TCLK3_B        16  
00368 #define PB0_TIOA3_B         0   
00369 #define PB1_TIOB3_B         1   
00371 #define PB17_TCLK4_B        17  
00372 #define PB2_TIOA4_B         2   
00373 #define PB18_TIOB4_B        18  
00375 #define PC22_TCLK5_B        22  
00376 #define PB3_TIOA5_B         3   
00377 #define PB19_TIOB5_B        19  
00379 
00380 
00382 #define PB30_PCK0_A         30  
00383 #define PC1_PCK0_B          1   
00384 #define PB31_PCK1_A         31  
00385 #define PC2_PCK1_B          2   
00387 
00388 
00390 #define PC10_A25_CFRNW_A    10  
00391 #define PC8_NCS4_CFCS0_A    8   
00392 #define PC9_NCS5_CFCS1_A    9   
00393 #define PC6_CFCE1_B         6   
00394 #define PC7_CFCE2_B         7   
00396 
00397 
00399 #define PC16_D16_A          16  
00400 #define PC17_D17_A          17  
00401 #define PC18_D18_A          18  
00402 #define PC19_D19_A          19  
00403 #define PC20_D20_A          20  
00404 #define PC21_D21_A          21  
00405 #define PC22_D22_A          22  
00406 #define PC23_D23_A          23  
00407 #define PC24_D24_A          24  
00408 #define PC25_D25_A          25  
00409 #define PC26_D26_A          26  
00410 #define PC27_D27_A          27  
00411 #define PC28_D28_A          28  
00412 #define PC29_D29_A          29  
00413 #define PC30_D30_A          30  
00414 #define PC31_D31_A          31  
00415 #define PC4_A23_A           4   
00416 #define PC5_A24_A           5   
00417 #define PC11_NCS2_A         11  
00418 #define PC14_NCS3_NANDCS_A  14  
00419 #define PC13_NCS6_B         13  
00420 #define PC12_NCS7_B         12  
00421 #define PC15_NWAIT_A        15  
00423 
00424 
00426 #define PC13_FIQ_A          13  
00427 #define PC12_IRQ0_A         12  
00428 #define PC15_IRQ1_B         15  
00429 #define PC14_IRQ2_B         14  
00431 
00432 
00434 #endif                          /* _ARCH_ARM_SAM9260_H_ */

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