00001 #ifndef _ARCH_ARM_AT91_US_H_
00002 #define _ARCH_ARM_AT91_US_H_
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00060
00063 #define US_CR_OFF 0x00000000
00064 #define US0_CR (USART0_BASE + US_CR_OFF)
00065 #define US1_CR (USART1_BASE + US_CR_OFF)
00066 #define US_RSTRX 0x00000004
00067 #define US_RSTTX 0x00000008
00068 #define US_RXEN 0x00000010
00069 #define US_RXDIS 0x00000020
00070 #define US_TXEN 0x00000040
00071 #define US_TXDIS 0x00000080
00072 #define US_RSTSTA 0x00000100
00073 #define US_STTBRK 0x00000200
00074 #define US_STPBRK 0x00000400
00075 #define US_STTTO 0x00000800
00076 #define US_SENDA 0x00001000
00078
00079
00081 #define US_MR_OFF 0x00000004
00082 #define US0_MR (USART0_BASE + US_MR_OFF)
00083 #define US1_MR (USART1_BASE + US_MR_OFF)
00085 #define US_CLKS 0x00000030
00086 #define US_CLKS_MCK 0x00000000
00087 #define US_CLKS_MCK8 0x00000010
00088 #define US_CLKS_SCK 0x00000020
00089 #define US_CLKS_SLCK 0x00000030
00091 #define US_CHRL 0x000000C0
00092 #define US_CHRL_5 0x00000000
00093 #define US_CHRL_6 0x00000040
00094 #define US_CHRL_7 0x00000080
00095 #define US_CHRL_8 0x000000C0
00097 #define US_SYNC 0x00000100
00099 #define US_PAR 0x00000E00
00100 #define US_PAR_EVEN 0x00000000
00101 #define US_PAR_ODD 0x00000200
00102 #define US_PAR_SPACE 0x00000400
00103 #define US_PAR_MARK 0x00000600
00104 #define US_PAR_NO 0x00000800
00105 #define US_PAR_MULTIDROP 0x00000C00
00107 #define US_NBSTOP 0x00003000
00108 #define US_NBSTOP_1 0x00000000
00109 #define US_NBSTOP_1_5 0x00001000
00110 #define US_NBSTOP_2 0x00002000
00112 #define US_CHMODE 0x0000C000
00113 #define US_CHMODE_NORMAL 0x00000000
00114 #define US_CHMODE_AUTOMATIC_ECHO 0x00004000
00115 #define US_CHMODE_LOCAL_LOOPBACK 0x00008000
00116 #define US_CHMODE_REMOTE_LOOPBACK 0x0000C000
00118 #define US_MODE9 0x00020000
00120 #define US_CLKO 0x00040000
00122
00123
00125 #define US_CSR_OFF 0x00000014
00126 #define US0_CSR (USART0_BASE + US_CSR_OFF)
00127 #define US1_CSR (USART1_BASE + US_CSR_OFF)
00129 #define US_IER_OFF 0x00000008
00130 #define US0_IER (USART0_BASE + US_IER_OFF)
00131 #define US1_IER (USART1_BASE + US_IER_OFF)
00133 #define US_IDR_OFF 0x0000000C
00134 #define US0_IDR (USART0_BASE + US_IDR_OFF)
00135 #define US1_IDR (USART1_BASE + US_IDR_OFF)
00137 #define US_IMR_OFF 0x00000010
00138 #define US0_IMR (USART0_BASE + US_IMR_OFF)
00139 #define US1_IMR (USART1_BASE + US_IMR_OFF)
00141 #define US_RXRDY 0x00000001
00142 #define US_TXRDY 0x00000002
00143 #define US_RXBRK 0x00000004
00144 #define US_ENDRX 0x00000008
00145 #define US_ENDTX 0x00000010
00146 #define US_OVRE 0x00000020
00147 #define US_FRAME 0x00000040
00148 #define US_PARE 0x00000080
00149 #define US_TIMEOUT 0x00000100
00150 #define US_TXEMPTY 0x00000200
00156 #define AT91_US_BAUD(baud) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
00157
00161 #define US_RHR_OFF 0x00000018
00162 #define US0_RHR (USART0_BASE + US_RHR_OFF)
00163 #define US1_RHR (USART1_BASE + US_RHR_OFF)
00165
00166
00168 #define US_THR_OFF 0x0000001C
00169 #define US0_THR (USART0_BASE + US_THR_OFF)
00170 #define US1_THR (USART1_BASE + US_THR_OFF)
00172
00173
00175 #define US_BRGR_OFF 0x00000020
00176 #define US0_BRGR (USART0_BASE + US_BRGR_OFF)
00177 #define US1_BRGR (USART1_BASE + US_BRGR_OFF)
00179
00180
00182 #define US_RTOR_OFF 0x00000024
00183 #define US0_RTOR (USART0_BASE + US_RTOR_OFF)
00184 #define US1_RTOR (USART1_BASE + US_RTOR_OFF)
00186
00187
00189 #define US_TTGR_OFF 0x00000028
00190 #define US0_TTGR (USART0_BASE + US_TTGR_OFF)
00191 #define US1_TTGR (USART1_BASE + US_TTGR_OFF)
00193
00194
00196 #define US_FIDI_OFF 0x00000040
00197 #define US0_FIDI (USART0_BASE + US_FIDI_OFF)
00198 #define US1_FIDI (USART1_BASE + US_FIDI_OFF)
00200
00201
00203 #define US_NER_OFF 0x00000044
00204 #define US0_NER (USART0_BASE + US_NER_OFF)
00205 #define US1_NER (USART1_BASE + US_NER_OFF)
00207
00208
00210 #define US_IF_OFF 0x0000004C
00211 #define US0_IF (USART0_BASE + US_IF_OFF)
00212 #define US1_IF (USART1_BASE + US_IF_OFF)
00214
00215 #if defined(USART_HAS_PDC)
00216
00219 #define US0_RPR (USART0_BASE + PERIPH_RPR_OFF)
00220 #define US1_RPR (USART1_BASE + PERIPH_RPR_OFF)
00222
00223
00225 #define US0_RCR (USART0_BASE + PERIPH_RCR_OFF)
00226 #define US1_RCR (USART1_BASE + PERIPH_RCR_OFF)
00228
00229
00231 #define US0_TPR (USART0_BASE + PERIPH_TPR_OFF)
00232 #define US1_TPR (USART1_BASE + PERIPH_TPR_OFF)
00234
00235
00237 #define US0_TCR (USART0_BASE + PERIPH_TCR_OFF)
00238 #define US1_TCR (USART1_BASE + PERIPH_TCR_OFF)
00240
00241 #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
00242 #define US0_RNPR (USART0_BASE + PERIPH_RNPR_OFF)
00243 #define US1_RNPR (USART1_BASE + PERIPH_RNPR_OFF)
00244 #define US0_RNCR (USART0_BASE + PERIPH_RNCR_OFF)
00245 #define US1_RNCR (USART1_BASE + PERIPH_RNCR_OFF)
00246 #endif
00247
00248 #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
00249 #define US0_TNPR (USART0_BASE + PERIPH_TNPR_OFF)
00250 #define US1_TNPR (USART1_BASE + PERIPH_TNPR_OFF)
00251 #define US0_TNCR (USART0_BASE + PERIPH_TNCR_OFF)
00252 #define US1_TNCR (USART1_BASE + PERIPH_TNCR_OFF)
00253 #endif
00254
00255 #if defined(PERIPH_PTCR_OFF)
00256 #define US0_PTCR (USART0_BASE + PERIPH_PTCR_OFF)
00257 #define US1_PTCR (USART1_BASE + PERIPH_PTCR_OFF)
00258 #endif
00259
00260 #if defined(PERIPH_PTSR_OFF)
00261 #define US0_PTSR (USART0_BASE + PERIPH_PTSR_OFF)
00262 #define US1_PTSR (USART1_BASE + PERIPH_PTSR_OFF)
00263 #endif
00264
00265 #endif
00266
00270 #endif